Fujitsu Recording Equipment MB15E07SL User Manual

FUJITSU SEMICONDUCTOR  
DATA SHEET  
DS04-21358-4E  
ASSP  
Single Serial Input  
PLL Frequency Synthesizer  
On-chip 2.5 GHz Prescaler  
MB15E07SL  
DESCRIPTION  
TheFujitsuMB15E07SLisaserialinputPhaseLockedLoop(PLL)frequencysynthesizerwitha2.5GHzprescaler.  
The 2.5 GHz prescaler has a dual modulus division ratio of 32/33 or 64/65 enabling pulse swallowing operation.  
The supply voltage range is between 2.4 V and 3.6 V. The MB15E07SL uses the latest BiCMOS process, as a  
result the supply current is typically 3.5 mA at 2.7 V. A refined charge pump supplies well-balanced output currents  
of 1.5 mA and 6 mA. The charge pump current is selectable by serial data.  
MB15E07SL is ideally suited for wireless mobile communications, such as GSM (Global System for Mobile  
Communications) and PCS.  
FEATURES  
• High frequency operation: 2.5 GHz Max  
• Low power supply voltage: VCC = 2.4 to 3.6 V  
• Ultra Low power supply current: ICC = 3.5 mA Typ (VCC = Vp = 2.7 V, Ta = +25°C, in locking state)  
ICC = 4.0 mA Typ (VCC = Vp = 3.0 V, Ta = +25°C, in locking state)  
• Direct power saving function: Power supply current in power saving mode  
Typ 0.1 µA (VCC = Vp = 3.0 V, Ta = +25°C), Max 10 µA (VCC = Vp = 3.0 V)  
(Continued)  
PACKAGES  
16-pin plastic SSOP  
16-pad plastic BCC  
(FPT-16P-M05)  
(LCC-16P-M06)  
 
MB15E07SL  
PIN DESCRIPTIONS  
Pin no.  
Pin  
I/O  
Descriptions  
name  
SSOP  
BCC  
16  
1
1
2
3
4
OSCIN  
OSCOUT  
VP  
I
Programmable reference divider input. Connection to a TCXO.  
Oscillator output.  
O
2
Power supply voltage input for the charge pump.  
Power supply voltage input.  
3
VCC  
Charge pump output.  
Phase of the charge pump can be selected via programming of the FC bit.  
5
4
DO  
O
6
7
5
6
GND  
Xfin  
I
Ground.  
Prescaler complementary input, which should be grounded via a capacitor.  
Prescaler input.  
8
7
fin  
Clock  
Data  
LE  
I
I
I
I
Connection to an external VCO should be done via AC coupling.  
Clock input for the 19-bit shift register.  
Data is shifted into the shift register on the rising edge of the clock.  
(Open is prohibited.)  
9
8
Serial data input using binary code.  
The last bit of the data is a control bit. (Open is prohibited.)  
10  
11  
9
Load enable signal input. (Open is prohibited.)  
When LE is set high, the data in the shift register is transferred to a latch  
according to the control bit in the serial data.  
10  
Power saving mode control. This pin must be set at “L” at Power-ON.  
(Open is prohibited.)  
PS = “H”; Normal mode  
12  
13  
14  
11  
12  
13  
PS  
ZC  
I
I
PS = “L”; Power saving mode  
Forced high-impedance control for the charge pump (with internal pull up  
resistor.)  
ZC = “H”; Normal Do output.  
ZC = “L”; Do becomes high impedance.  
Lock detect signal output (LD)/phase comparator monitoring output (fout).  
The output signal is selected via programming of the LDS bit.  
LDS = “H”; outputs fout (fr/fp monitoring output)  
LD/fout  
O
LDS = “L”; outputs LD (“H” at locking, “L” at unlocking.)  
Phase comparator N-channel open drain output for an external charge  
pump. Phase can be selected via programming of the FC bit.  
15  
16  
14  
15  
φP  
φR  
O
O
Phase comparator CMOS output for an external charge pump. Phase can  
be selected via programming of the FC bit.  
3
 
MB15E07SL  
BLOCK DIAGRAM  
fr  
(16)  
1
(15)  
16  
OSCIN  
φR  
φP  
Reference  
oscillator  
circuit  
Phase  
comparator  
(14)  
15  
(1)  
2
OSCOUT  
Lock  
detector  
SW FC  
CS  
LDS  
Binary 14-bit  
reference counter  
(13)  
14 LD/fout  
(2)  
3
LD/fr/fp  
selector  
14-bit latch  
. .  
4-bit latch  
VP  
fp  
C
19-bit shift register  
N
T
(12)  
13  
(3)  
4
ZC  
PS  
VCC  
. . .  
. . .  
7-bit latch  
11-bit latch  
(11)  
12  
(4)  
5
Intermittent  
mode control  
(power save)  
DO  
Binary 11-bit  
programmable  
counter  
Binary 7-bit  
swallow counter  
(10)  
11 LE  
(5)  
6
GND  
1-bit  
control  
latch  
(9)  
10  
(6)  
7
Data  
Xfin  
fin  
MD  
Prescaler  
32/33  
64/65  
(7)  
8
(8)  
9
Clock  
: SSOP  
) : BCC  
(
4
 
MB15E07SL  
ABSOLUTE MAXIMUM RATINGS  
Rating  
Parameter  
Symbol  
Condition  
Unit  
Remark  
Min  
–0.5  
VCC  
Max  
4.0  
VCC  
VP  
V
V
Power supply voltage  
Input voltage  
6.0  
VI  
–0.5  
GND  
GND  
–55  
VCC +0.5  
VCC  
V
VO  
Except Do  
V
Output voltage  
VO  
Do  
VP  
V
Storage temperature  
Tstg  
+125  
°C  
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,  
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.  
RECOMMENDED OPERATING CONDITIONS  
Value  
Parameter  
Symbol  
Unit  
Remark  
Min  
2.4  
Typ  
3.0  
Max  
3.6  
VCC  
VP  
VI  
V
V
Power supply voltage  
VCC  
5.5  
Input voltage  
GND  
–40  
VCC  
+85  
V
Operating temperature  
Ta  
°C  
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the  
semiconductor device. All of the device’s electrical characteristics are warranted when the device is  
operated within these ranges.  
Always use semiconductor devices within their recommended operating condition ranges. Operation  
outside these ranges may adversely affect reliability and could result in device failure.  
No warranty is made with respect to uses, operating conditions, or combinations not represented on  
the data sheet. Users considering application outside the listed conditions are advised to contact their  
FUJITSU representatives beforehand.  
5
 
MB15E07SL  
ELECTRICAL CHARACTERISTICS  
(VCC = 2.4 to 3.6 V, Ta = 40 to +85°C)  
Value  
Unit  
Parameter  
Symbol  
Condition  
Min  
Typ  
Max  
fin = 2500 MHz, VCC = VP = 2.7 V  
(VCC = VP = 3.0 V)  
3.5  
(4.0)  
0.1*2  
Power supply current*1  
Power saving current  
ICC  
mA  
*1  
IPS  
fIN  
ZC = “H” or open  
700  
3
10  
2500  
40  
µA  
fin  
MHz  
MHz  
Operating frequency  
OSCIN OSCIN  
50 system  
*3  
fin  
Pfin (Refer to the measurement  
circuit.)  
–15  
+2  
dBm  
Vp-p  
Input sensitivity  
*3  
OSCIN  
VOSC  
0.5  
VCC  
“H” level input voltage  
“L” level input voltage  
Data,  
Clock,  
LE,PS,  
ZC  
VIH  
VCC × 0.7  
V
VIL  
VCC × 0.3  
*4  
“H” level input current  
“L” level input current  
Data,  
Clock,  
LE, PS  
IIH  
–1.0  
–1.0  
+1.0  
+1.0  
µA  
µA  
*4  
IIL  
“H” level input current  
“L” level input current  
“H” level input current  
“L” level input current  
“L” level output voltage  
“H” level output voltage  
“L” level output voltage  
“H” level output voltage  
“L” level output voltage  
IIH  
0
–100  
–1.0  
–100  
+100  
0
OSCIN  
*4  
IIL  
*4  
IIH  
+1.0  
0
ZC  
µA  
V
*4  
IIL  
Pull up input  
φP  
VOL  
VOH  
Open drain output  
0.4  
VCC = VP = 3.0 V, IOH = –1 mA  
VCC = VP = 3.0 V, IOL = 1 mA  
VCC – 0.4  
φR,  
LD/fout  
V
VOL  
0.4  
VDOH  
VDOL  
VCC = VP = 3.0 V, IDOH = –0.5 mA VP – 0.4  
Do  
V
VCC = VP = 3.0 V, IDOL = 0.5 mA  
0.4  
High impedance cutoff  
current  
VCC = VP = 3.0 V,  
VOFF = 0.5 V to VP – 0.5 V  
Do  
IOFF  
2.5  
nA  
“L” level output current  
“H” level output current  
“L” level output current  
φP  
IOL  
IOH  
IOL  
Open drain output  
1.0  
–1.0  
mA  
φR,  
LD/fout  
mA  
mA  
1.0  
CS bit = “H”  
–6.0  
–1.5  
6.0  
1.5  
3
*4  
VCC = 3 V,  
“H” level output current  
“L” level output current  
IDOH  
CS bit = “L”  
CS bit = “H”  
CS bit = “L”  
VP = 3 V,  
VDO = VP/2  
Ta = +25°C  
Do  
IDOL  
*5  
IDOL/IDOH IDOMT  
VDO = VP/2  
%
%
%
Charge pump current  
rate  
*6  
IDOVD  
vs VDO  
vs Ta  
0.5 V VDO VP – 0.5 V  
– 40°C Ta +85°C  
10  
10  
*7  
IDOTA  
*1 : Conditions; fosc = 12 MHz, Ta = +25°C, in locking state.  
*2 : VCC = VP = 3.0 V, fosc = 12.8 MHz, Ta = +25°C, in power saving mode  
6
 
MB15E07SL  
*3 : AC coupling. 1000 pF capacitor is connected under the condition of Min operating frequency.  
*4 : The symbol “–” (minus) means direction of current flow.  
*5 : VCC = VP = 3.0 V, Ta = +25°C (|I3| – |I4|) / [(|I3| + |I4|) /2] × 100(%)  
*6 : VCC = VP = 3.0 V, Ta = +25°C [(|I2| – |I1|) /2] / [(|I1| + |I2|) /2] × 100(%) (Applied to each IDOL, IDOH)  
*7 : VCC = VP = 3.0 V, VDO = VP/2 (|IDO(85°C) – IDO(–40°C)| /2) / (|IDO(85°C) + IDO(–40°C)| /2) × 100(%) (Applied to each IDOL, IDOH)  
I1  
I3  
I2  
IDOL  
IDOH  
I4  
I2  
I1  
0.5  
Vp/2  
Vp 0.5 V  
Vp  
Charge Pump Output Voltage (V)  
7
 
MB15E07SL  
FUNCTIONAL DESCRIPTION  
1. Pulse Swallow Function  
The divide ratio can be calculated using the following equation:  
fVCO = [(M × N) + A] × fOSC ÷ R (A < N)  
fVCO : Output frequency of external voltage controlled oscillator (VCO)  
N
A
: Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)  
: Preset divide ratio of binary 7-bit swallow counter (0 A 127)  
fOSC : Output frequency of the reference frequency oscillator  
R
M
: Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)  
: Preset divide ratio of modulus prescaler (32 or 64)  
2. Serial Data Input  
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference  
divider and the programmable divider separately.  
Binary serial data is entered through the Data pin.  
One bit of data is shifted into the shift register on the rising edge of the Clock. When the LE signal pin is taken  
high, stored data is latched according to the control bit data as follows:  
Table 1. Control Bit  
Control bit (CNT)  
Destination of serial data  
For the programmable reference divider  
For the programmable divider  
H
L
(1) Shift Register Configuration  
Programmable Reference Counter  
LSB  
1
MSB  
Data Flow  
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19  
C
N
T
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
R
R
R
R
R
10 11 12 13 14 SW FC LDS CS  
CNT  
: Control bit  
[Table 1]  
R1 to R14 : Divide ratio setting bit for the programmable reference counter (3 to 16,383)  
[Table 2]  
[Table 5]  
[Table 8]  
[Table 7]  
[Table 6]  
SW  
FC  
LDS  
CS  
: Divide ratio setting bit for the prescaler (32/33 or 64/65)  
: Phase control bit for the phase comparator  
: LD/fOUT signal select bit  
: Charge pump current select bit  
Note: Start data input with MSB first.  
8
 
MB15E07SL  
Programmable Counter  
MSB  
LSB  
1
Data Flow  
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19  
C
N
T
A
1
A
2
A
3
A
4
A
5
A
6
A
7
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N
N
10 11  
CNT  
: Control bit  
[Table 1]  
[Table 3]  
[Table 4]  
N1 to N11 : Divide ratio setting bits for the programmable counter (3 to 2,047)  
A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127)  
Note: Data input with MSB first.  
Table 2. Binary 14-bit Programmable Reference Counter Data Setting  
Divide ratio (R) R14 R13 R12 R11 R10 R9  
R8  
0
R7  
0
R6  
0
R5  
R4  
0
R3  
0
R2  
1
R1  
1
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
0
0
0
0
1
0
0
16383  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note : Divide ratio less than 3 is prohibited.  
Table 3. Binary 11-bit Programmable Counter Data Setting  
Divide ratio (N)  
N11  
N10  
N9  
0
N8  
0
N7  
0
N6  
N5  
0
N4  
0
N3  
N2  
1
N1  
3
0
0
0
0
0
0
0
1
1
0
4
0
0
0
0
0
0
2047  
1
1
1
1
1
1
1
1
1
1
1
Note : Divide ratio less than 3 is prohibited.  
Table 4. Binary 7-bit Swallow Counter Data Setting  
Divide ratio (A)  
A7  
0
A6  
0
A5  
A4  
0
A3  
0
A2  
A1  
0
1
0
0
0
0
0
1
0
0
0
0
127  
1
1
1
1
1
1
1
9
 
MB15E07SL  
Table 5. Prescaler Data Setting  
SW  
Prescaler divide ratio  
H
L
32/33  
64/65  
Table 6. Charge Pump Current Setting  
CS  
Current value  
±6.0 mA  
H
L
±1.5 mA  
Table 7. LD/fout Output Select Data Setting  
LDS  
LD/fOUT output signal  
H
L
fout signal  
LD signal  
(2) Relation between the FC Input and Phase Characteristics  
The FC bit changes the phase characteristics of the phase comparator. Both the internal charge pump output  
level (DO) and the phase comparator output (φR, φP) are reversed according to the FC bit. Also, the monitor pin  
(fOUT) output is controlled by the FC bit. The relationship between the FC bit and each of DO, φR, and φP is shown  
below.  
Table 8. FC Bit Data Setting (LDS = “H”)  
FC = High  
FC = Low  
φR  
DO  
H
φR  
φP  
L
LD/fout  
DO  
L
φP  
Z*  
L
LD/fout  
fr > fP  
fr < fP  
fr = fP  
L
H
L
H
L
L
L
Z*  
Z*  
fout = fr  
H
fout = fp  
Z*  
Z*  
Z*  
* : High-Z  
10  
 
MB15E07SL  
When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics.  
* : When the LPF and VCO characteristics are similar  
to (1), set FC bit high.  
(1)  
* : When the VCO characteristics are similar to (2), set  
FC bit low.  
VCO  
Output  
Frequency  
PLL  
LPF  
VCO  
(2)  
LPF Output Voltage  
3. Do Output Control  
Table 9. ZC Pin Setting  
ZC pin  
Do output  
H
L
Normal output  
High impedance  
4. Power Saving Mode (Intermittent Mode Control Circuit)  
Table 10. PS Pin Setting  
PS pin  
Status  
H
L
Normal mode  
Power saving mode  
The intermittent mode control circuit reduces the PLL power consumption.  
By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See  
the Electrical Characteristics chart for the specific value.  
The phase detector output, Do, becomes high impedance.  
For the signal PLL, the lock detector, LD, remains high, indicating a locked condition.  
Setting the PS pin high, releases the power saving mode, and the device works normally.  
The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation.  
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is  
because  
of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can  
cause a major change in the comparator output, resulting in a VCO frequency jump and an increase in lockup  
time.  
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error  
signal from the phase detector when it returns to normal operation.  
When power (VCC) is first applied, the device must be in standby mode, PS = Low, for at least 1 µs.  
11  
 
MB15E07SL  
Note : PS pin must be set “L” for Power-ON.  
OFF  
ON  
tV 1 µs  
VCC  
Clock  
Data  
LE  
tPS 100 ns  
PS  
(1)  
(2)  
(3)  
(1) PS = L (power saving mode) at Power ON  
(2) Set serial data 1 µs later after power supply remains stable (VCC > 2.2 V).  
(3) Release power saving mode (PS: L H) 100 ns later after setting serial data.  
12  
 
MB15E07SL  
SERIAL DATA INPUT TIMING  
1st data  
2nd data  
Control bit Invalid data  
Data  
MSB  
LSB  
Clock  
t1  
t2  
t3  
t6  
t7  
LE  
t4  
t5  
On the rising edge of the clock, one bit of data is transferred into the shift register.  
Parameter Min  
Typ  
Max Unit  
Parameter Min  
Typ  
Max Unit  
t1  
t2  
t3  
t4  
20  
20  
30  
30  
ns  
ns  
ns  
ns  
t5  
t6  
t7  
100  
20  
ns  
ns  
ns  
100  
Note : LE should be “L” when the data is transferred into the shift register.  
13  
 
MB15E07SL  
PHASE COMPARATOR OUTPUT WAVEFORM  
fr  
fp  
tWU  
tWL  
LD  
[FC = “H”]  
DO  
[FC = “L”]  
DO  
Notes : Phase error detection range: –2π to +2π  
Pulses on Do signal during locked state are output to prevent dead zone.  
LD output becomes low when phase is tWU or more. LD output becomes high when phase error  
is tWL or less and continues to be so for three cycles or more.  
tWU and tWL depend on OSCIN input frequency.  
tWU > 2/fosc (s) (e. g. tWU > 156.3 ns, fosc = 12.8 MHz)  
tWU < 4/fosc (s) (e. g. tWL < 312.5 ns, fosc = 12.8 MHz)  
LD becomes high during the power saving mode (PS = “L”).  
14  
 
MB15E07SL  
MEASURMENT CIRCUIT (for Measuring Input Sensitivity fin/OSCIN)  
1000 pF  
0.1 µF  
1000 pF  
0.1 µF  
1000 pF  
S • G  
S • G  
fin  
8
Xfin GND DO  
VCC  
VP OSCOUT OSCIN  
50 Ω  
50 Ω  
7
6
5
4
3
2
1
9
10  
11  
12  
13  
14  
15  
16  
Clock Data LE  
φP  
φR  
PS  
ZC LD/fout  
VCC  
Oscilloscope  
Controller (setting divide ratio)  
Note: SSOP-16  
15  
 
MB15E07SL  
TYPICAL CHARACTERISTICS  
1. fin input sensitivity  
Input sensitivity Input frequency (Prescaler: 64/65)  
Ta = +25 °C  
10  
0
SPEC  
10  
20  
30  
40  
50  
VCC = 2.4 V  
VCC = 3.0 V  
VCC = 3.6 V  
0
200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000  
Input frequency fin (MHz)  
Input sensitivity Input frequency (Prescaler: 32/33)  
Ta = +25 °C  
10  
0
SPEC  
10  
20  
30  
40  
50  
VCC = 2.7 V  
VCC = 3.0 V  
VCC = 3.6 V  
0
200  
400  
600  
800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000  
Input frequency fin (MHz)  
16  
 
MB15E07SL  
2. OSCIN input sensitivity  
Input sensitivity Input frequency  
Ta = +25 °C  
10  
SPEC  
0
10  
20  
30  
40  
50  
VCC = 2.4 V  
VCC = 3.0 V  
VCC = 3.6 V  
60  
0
50  
100  
150  
200  
Input frequency fOSC (MHz)  
17  
 
MB15E07SL  
3. Do output current  
1.5 mA mode  
VDO - IDO  
Ta = +25°C  
VCC = 3.0 V  
Vp = 3.0 V  
10.00  
2.000  
/div  
IDOL  
0
IDOH  
–10.00  
0
4.800  
.6000/div  
Charge pump output voltage VDO (V)  
6.0 mA mode  
VDO - IDO  
Ta = +25°C  
VCC = 3.0 V  
Vp = 3.0 V  
10.00  
IDOL  
2.000  
/div  
0
IDOH  
–10.00  
0
4.800  
.6000/div  
Charge pump output voltage VDO (V)  
18  
 
MB15E07SL  
4. fin input impedance  
1 : 12.646 Ω  
–57.156 Ω  
1 GHz  
22.156 Ω  
–12.136 Ω  
1.5 GHz  
2 :  
3 :  
4 :  
4
33.805 Ω  
11.869 Ω  
2 GHz  
23.715 Ω  
8.9629 Ω  
2.5 GHz  
3
2
1
START  
500.000 000 MHz  
STOP 2 500.000 000 MHz  
5. OSCIN input impedance  
1 : 9.917 Ω  
–3.643 Ω  
3 MHz  
3.7903 Ω  
–4.812 Ω  
10 MHz  
2 :  
3 :  
4 :  
1.574 Ω  
–3.4046 Ω  
20 MHz  
4
3
2
1
453.12 Ω  
–1.9213 Ω  
40 MHz  
START  
1.000 000 MHz  
STOP  
50.000 000 MHz  
19  
 
MB15E07SL  
REFERENCE INFORMATION  
Test Circuit  
fVCO = 810.45 MHz VCC =VP = 3.0 V  
KV = 17 MHz/V  
fr = 25 kHz  
fOSC = 14.4 MHz  
VVCO = 2.3 V  
Ta = +25 °C  
CP : 6 mA mode  
S.G  
OSCIN  
fin  
LPF  
Do  
LPF  
9.1 kΩ  
4.2 kΩ  
0.047 µF  
4700 pF  
1500 pF  
Spectrum  
Analyzer  
VCO  
PLL Reference Leakage  
ATT 10 dB  
25.0 kHz  
–78.0 dB  
REF –5.0 dBm  
10 dB/  
MKR  
RBW  
1 kHz  
SAMPLE  
VBW  
1 kHz  
SWP 1.0 s  
CENTER 810.000 MHz  
SPAN 200 kHz  
ATT 10 dB  
PLL Phase Noise  
2.28 kHz  
–53.1 dB  
REF –5.0 dBm  
10 dB/  
MKR  
RBW  
100 Hz  
SAMPLE  
VBW  
100 Hz  
SWP 10 s  
CENTER 810.000 MHz  
SPAN 20.0 kHz  
(Continued)  
20  
 
MB15E07SL  
(Continued)  
PLL Lock Up time  
1.30 ms  
PLL Lock Up time  
826 MH810 MHz within ± 1 kHz  
810 MH826 MHz within ± 1 kHz  
HchLch  
1.28 ms  
LchHch  
846.000 MHz  
838.000 MHz  
826.000 MHz  
806.000 MHz  
818.000 MHz  
798.000 MHz  
500.0 µs/div  
500.0 µs/div  
810.004000MHz  
826.004000 MHz  
826.000000 MHz  
810.000000MHz  
809.996000MHz  
825.996000 MHz  
500.0 µs/div  
500.0 µs/div  
21  
 
MB15E07SL  
APPLICATION EXAMPLE  
VP  
10 kΩ  
12 kΩ  
OUTPUT  
VCO  
LPF  
12 kΩ  
10 kΩ  
Lock Det.  
From  
a controller  
φR  
φP  
ZC  
13  
LE  
11  
Data  
10  
Clock  
9
LD/fout  
14  
PS  
12  
16  
15  
MB15E07SL  
1
2
3
4
5
6
7
8
OSCOUT  
OSCIN  
VP  
GND  
fin  
DO  
Xfin  
VCC  
1000 pF  
1000 pF  
1000 pF  
0.1 µF  
0.1 µF  
TCXO  
VP: 5.5 V Max  
Notes : SSOP-16  
In case of using a crystal resonator, it is necessary to optimize matching between the crystal  
and this LSI, and perform detailed system evaluation. It is recommended to consult with a  
supplier of the crystal resonator. (Reference oscillator circuit provides its own bias, feedback  
resistor is 100 k(Typ).)  
22  
 
MB15E07SL  
USAGE PRECAUTIONS  
To protect against damage by electrostatic discharge, note the following handling precautions:  
-Store and transport devices in conductive containers.  
-Use properly grounded workstations, tools, and equipment.  
-Turn off power before inserting device into or removing device from a socket.  
-Protect leads with a conductive sheet when transporting a board-mounted device.  
ORDERING INFORMATION  
Part number  
MB15E07SLPFV1  
MB15E07SLPV1  
Package  
Remarks  
16-pin, Plastic SSOP  
(FPT-16P-M05)  
16-pad, Plastic BCC  
(LCC-16P-M06)  
23  
 
MB15E07SL  
PACKAGE DIMENSIONS  
Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max).  
Note 2) *2 : These dimensions do not include resin protrusion.  
Note 3) Pins width and pins thickness include plating thickness.  
Note 4) Pins width do not include tie bar cutting remainder.  
16-pin plastic SSOP  
(FPT-16P-M05)  
15.00±0.10(.197±.004)  
*
0.17±0.03  
(.007±.001)  
16  
9
2 4.40±0.10 6.40±0.20  
(.173±.004) (.252±.008)  
*
INDEX  
Details of "A" part  
1.25 +0.20  
–0.10  
(Mounting height)  
.049 +.008  
–.004  
1
8
LEAD No.  
"A"  
0.65(.026)  
0.24±0.08  
(.009±.003)  
M
0.13(.005)  
0~8˚  
0.10±0.10  
(.004±.004)  
(Stand off)  
0.50±0.20  
(.020±.008)  
0.25(.010)  
0.60±0.15  
(.024±.006)  
0.10(.004)  
C
2003 FUJITSU LIMITED F16013S-c-4-6  
Dimensions in mm (inches  
)
Note : The values in parentheses are reference values.  
(Continued)  
24  
 
MB15E07SL  
(Continued)  
16-pad plastic BCC  
(LCC-16P-M06)  
4.55±0.10  
(.179±.004)  
0.80(.031)MAX  
Mounting height  
3.40(.134)TYP  
0.65(.026)  
0.325±0.10  
(.013±.004)  
TYP  
0.40±0.10  
(.016±.004)  
14  
9
9
14  
0.80(.031)  
REF  
INDEX AREA  
3.40±0.10  
(.134±.004)  
2.45(.096)  
TYP  
1.15(.045)  
REF  
"B"  
"A"  
0.075±0.025  
(.003±.001)  
(Stand off)  
1.725(.068)  
REF  
1
6
6
1
Details of "A" part  
0.75±0.10  
Details of "B" part  
0.60±0.10  
(.024±.004)  
(.030±.004)  
0.05(.002)  
0.40±0.10  
0.60±0.10  
(.016±.004)  
(.024±.004)  
C
1999 FUJITSU LIMITED C16017S-1C-1  
Dimensions in mm (inches  
)
Note : The values in parentheses are reference values.  
25  
 
MB15E07SL  
FUJITSU LIMITED  
All Rights Reserved.  
The contents of this document are subject to change without notice.  
Customers are advised to consult with FUJITSU sales  
representatives before ordering.  
The information, such as descriptions of function and application  
circuit examples, in this document are presented solely for the  
purpose of reference to show examples of operations and uses of  
Fujitsu semiconductor device; Fujitsu does not warrant proper  
operation of the device with respect to use based on such  
information. When you develop equipment incorporating the  
device based on such information, you must assume any  
responsibility arising out of such use of the information. Fujitsu  
assumes no liability for any damages whatsoever arising out of  
the use of the information.  
Any information in this document, including descriptions of  
function and schematic diagrams, shall not be construed as license  
of the use or exercise of any intellectual property right, such as  
patent right or copyright, or any other right of Fujitsu or any third  
party or does Fujitsu warrant non-infringement of any third-party’s  
intellectual property right or other right by using such information.  
Fujitsu assumes no liability for any infringement of the intellectual  
property rights or other rights of third parties which would result  
from the use of information contained herein.  
The products described in this document are designed, developed  
and manufactured as contemplated for general use, including  
without limitation, ordinary industrial use, general office use,  
personal use, and household use, but are not designed, developed  
and manufactured as contemplated (1) for use accompanying fatal  
risks or dangers that, unless extremely high safety is secured, could  
have a serious effect to the public, and could lead directly to death,  
personal injury, severe physical damage or other loss (i.e., nuclear  
reaction control in nuclear facility, aircraft flight control, air traffic  
control, mass transport control, medical life support system, missile  
launch control in weapon system), or (2) for use requiring  
extremely high reliability (i.e., submersible repeater and artificial  
satellite).  
Please note that Fujitsu will not be liable against you and/or any  
third party for any claims or damages arising in connection with  
above-mentioned uses of the products.  
Any semiconductor devices have an inherent chance of failure. You  
must protect against injury, damage or loss from such failures by  
incorporating safety design measures into your facility and  
equipment such as redundancy, fire protection, and prevention of  
over-current levels and other abnormal operating conditions.  
If any products described in this document represent goods or  
technologies subject to certain restrictions on export under the  
Foreign Exchange and Foreign Trade Law of Japan, the prior  
authorization by Japanese government will be required for export  
of those products from Japan.  
F0306  
FUJITSU LIMITED Printed in Japan  
 

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